# Introduction

For the Projektseminar I designed, built and tested an evaluation platform for an ADC ASIC designed at the Fachbereich Integrierte Elektronische Systeme by MSc. Harish Balasubramaniam. The platform has to supply all necessary voltages, clock and control signals and breakout the signals that need to be measured. To be able to swap out broken parts and make the design reusable a modular approach has been implemented. The modules were arranged around a main board that carries the device under test (DUT).

# High Level Design

## Rationale

When a complex ASIC, after many months of simulating and tweaking, finally gets manufactured its performance has to be checked. Several measurements are made and the results compared to those from the simulations. Only then a verdict can be reached if the goals that were set for the design have been achieved. However, to conduct these measurements, support circuitry surrounding the device-under-test (DUT) is needed. For this seminar I went through the steps necessary to design this kind of circuits for a complex ASIC designed at the Fachgebiet Integrierte Elektronische Systeme. All circuits designed over the course of the seminar were specified in a way that they do not limit the performance of the DUT. The particular fitness of each module was verified through appropriate measurements.

## Block Diagram

As can be seen in the block diagram, the main board is the center-piece of the system. It carries the DUT and breaks out supply voltages, additional voltages and I/O. It also includes the circuitry to drive the ADC's differential inputs with a single-ended signal coming from a function generator. It is itself connected to a Xilinx FPGA development board, which is used to generate the necessary digital control signals and read back the data. The two power-supply boards provide the core voltages for the ASIC. The DAC board generates twelve reference voltages needed for the ASIC's internal circuitry. Finally the clock board receives a reference clock from the FPGA board. This clock signal is converted from LVDS to LVCMOS levels.

# Modules

## Clock Module

The clock board is based on the ICS8308I1 by IDT. This clock fanout buffer offers eight low-jitter LVCMOS outputs and a differential as well as an LVCMOS input. It is specified up to $$350~\text{MHz}$$. For maximum performance the necessary $$3.3~\text{V}$$ and $$2.5~\text{V}$$ rails are generated on-board. The board also includes an $$80~\text{MHz}$$ oscillator that can supply a test-clock to the LVCMOS input of the ICS8308I. The clock board also includes built-in delay lines ranging from 0 ps to $$300~\text{ps}$$ in $$50~\text{ps}$$ steps.

## DAC Module

The DAC module outputs 12 precision reference voltages. These are generated by two I²C compatible 16-Bit digital-to-analog converters (DAC). The two DACs used on this board are the AD56692 and AD56963 from Analog Devices. These DACs come with an integrated reference voltage of $$2.5~\text{V}$$ for an output from $$0~\text{V}$$ to $$2.5~\text{V}$$. Two of the AD5696' outputs are scaled to a range of $$0-1.0~\text{V}$$ for an even higher resolution. A resistor voltage divider is used to scale the voltages and its output is buffered by an ADA4528-24 precision, ultralow noise OpAmp. For these outputs one LSB equals about $$15~\mu \text{V}$$.

Particular attention was paid to the power supply design for the DAC board. Each DAC has its own dedicated LT17635 low noise linear regulator. The analog and logic supply pins of the AD5696 are decoupled by an RC-filter to prevent logic noise coupling into the analog supply. Also a split ground plane was used, separating logic and analog ground.

The DAC module can be programmed via the I²C lines on its communication connector. The outputs are accessible through a shielded SUB-D 25-pin connector.

## Power Supply Module

The power supply module is based on the LT30856 by Linear Technology. The output voltage of this low dropout linear regulator can be programmed with just one resistor, making it easy to control it with a digital potentiometer. It also has low output noise of just $$40~\mu \text{V}_{RMS}$$ ($$10~\text{Hz}$$ to $$100~\text{kHz}$$). The digital potentiometer used is the MCP4552-104E7 from Microchip, which is an I²C device. To control the output voltage and current the INA219B8 was used, it can be read out trough I²C as well.

The input voltage first goes into a pre-regulator and is lowered to $$1.82~\text{V}$$. After this regulator comes a programmable regulator, which is followed by a current shunt that is connected to the INA219. Finally a relay connects the output voltage to the header which plugs into the main board. The relay can be used to implement a specific power-up sequence for the DUT.

The communication connector on the power supply board is the same as the one on the DAC board, making it easy to connect all board together on one bus.

## Main Board

The main board carries the device under test and connects to all the other modules as well as to the FPGA board. It also provides differential ADC input drivers and the $$2.5~\text{V}$$ I/O supply voltage.

Input signals for the board can be supplied as single-ended signals through two BNC connectors. On the board two AD84769 unity gain differential ADC drivers perform the single-ended to differential conversion. The common-mode voltage of these amplifiers is connected to the DAC module and thus programmable. To enable the signals to swing close to zero volts the amplifiers are supplied with $$\pm2.5~\text{V}$$. The negative voltage is derived from the positive supply by an LM266410 charge-pump inverter and regulated by an TPS7232511 negative linear regulator. The AD8476s are followed by a two-stage low-pass RC filter network. Their corner frequency can be changed through jumper settings.

As this is a mixed signal design, with precision DC voltages and high-frequency clock and data lines on the same board, a four layer PCB was used. The two outer layers carry as few signals as possible and were flooded with a ground plane. The ground plane acts as shield for the precision voltages and improves the signal integrity of the high-speed digital lines. Several critical signals were routed with matched trace lengths to ensure proper data transfer. All digital connections were placed on the left side of the board, all analog connections on the right. Digital and analog signals do not cross each other.

Using the communication connector on the main board the two PSU modules and the DAC module can be controlled from the FPGA board. This enables automated test setups.

# Results

## Clock module

The performance of the clock module was verified using a Tektronix TDS7404 $$4~\text{GHz}$$ oscilloscope. The differential clock input was connected to the clock output of a Xilinx ML505 FPGA evaluation board. Unfortunately the output signals from the clock module are far from a square wave. The possible causes for these signal integrity issues include ground bounce, insufficient decoupling and impedance mismatch. The root cause however could not be identified.

The actual delay times were measured using the TDS7404 oscilloscope, the values are shown in Table .

Calculated delay [ps] Measured delay [ps] Error [ps]
0 36.08 36.08 -
50 66.76 16.76 33.52%
100 96.00 4.00 4.00%
150 164.05 14.05 9.37%
200 214.63 14.63 7.32%
250 272.50 22.50 9.00%
300 316.92 16.92 5.64%

## DAC module

The resolution and accuracy of the DAC outputs were verified using a calibrated Hameg HM8112-2 6.5-digit multimeter. Multiple measurements were taken to check for linearity and offset. Also the noise was measured with an oscilloscope, however it was below the noise floor of the available unit.

## Power Supply Module

The power supply board has been tested at its maximum specified output current of $$500~\text{mA}$$ over the full output voltage range from $$0.5~\text{V}$$ to $$1.5~\text{V}$$. Under load the temperature of the pre-regulator - which is producing the most heat - reached $$100~\,^{\circ}\text{C}$$ and thus stayed well below the maximum allowable temperature of $$125~\,^{\circ}\text{C}$$ for the LT3085. The INA219B current shunt IC was tested successfully as well. The values measured by it were verified using the Hameg HM8112-2 multimeter.

The output noise of the circuit was below the noise floor of the available equipment.

## Main Board

For the main board the performance of the ADC driver was of interest. First of all the phase shift between the positive and negative differential outputs was measured using a Hameg HM8123 programmable counter. It was found to be between $$178.0\,^{\circ}$$ to $$180.5\,^{\circ}$$ for frequencies from $$1~\text{kHz}$$ and $$22~\text{kHz}$$.

The most important characteristic for the ADC driver however is the harmonic distortion and noise. For the measurement the Tektronix AFG3102 arbitrary waveform generator was used as a signal source, a TI THS4509 OpAmp evaluation board as buffer and the Tektronix RSA3303 spectrum analyzer for the actual measurement. The setup is illustrated in the Figure above. The resulting output spectrum can be seen above. As the spectrum clearly shows the output noise of the AD8476 is below the detectable threshold for most frequencies. The second harmonic is about $$80~\text{dB}$$ below the fundamental. The actual value is most likely even better, however it could not be measured as for the limitations of the setup.

# Conclusions

With the notable exception of the clock module the designed evaluation platform met its requirements. As of October 11th, 2013 it is used by MSc. Harish Balasubramaniam in the testing of his ADC chip. Preliminary tests are promising and all modules seem to be up to the task.

# Appendices

## Main Board Schematic (v10)

Note: The values for R1-R8 and C44-C59 have been changed.